The present invention relates generally to the field of bias temperature instability (BTI) in the circuits of an integrated circuit, and, more particularly to hardware and techniques minimizing adverse effects that can be caused by BTI.
BTI stress is a known phenomenon. Generally speaking: (i) BTI degrades the performance of the semiconductor material in transistors in a way that depends on the voltages (for example, high, low) and the source, gate and drain terminals; and (ii) BTI degradation is asymptotic in nature so that the longer a transistor is maintained in a high BTI stress voltage state, the less marginal BTI degradation will occur. It is also known that if certain electrically-proximate circuit components have different levels of BTI degradation, then this can cause poor performance, or even electrical malfunction. BTI degradation (and/or uneven distribution of BTI degradation among circuit components) has been recognized as a potential problem for nano-scale PFET (NBTI) and NFET (PBTI) transistors. One category of techniques for attempting to prevent adverse effects caused by BTI is to: (i) try to estimate (by analytical, rather than empirical, techniques) how much BTI degradation the various circuit components of a (generally large scale) circuitry set have undergone; and (ii) adjust duty cycles and/or otherwise “burn in” the circuitry with signals designed to even out the level of BTI degradation as among the various components of the circuitry set.
BTI has the following additional known characteristics: (i) a NFET (negative channel field effect transistor) device exhibits an increase in non-mobile negative charge during symmetric (source=drain) stress, and this shift results in larger magnitude threshold voltages over time; (ii) PFET (positive channel field effect transistor) device exhibits an increase in non-mobile positive charge during symmetric (source=drain) stress, and this shift results in larger magnitude threshold voltages over time; and (iii) for a matched PFET pair, NBTI (negative-bias temperature instability) can introduce a mismatch shift in the following ways: (a) when the gate biases or the equivalent time of the gate biases are not equal in the two PFET devices, this inequality will induce a systematic mismatch in Vt (threshold voltage), (b) process variations across the chip, such as tox, will cause systematic mismatch shifts between widely spaced devices, and (c) for closely spaced devices with equal gate biases, NBTI will induce a random mismatch shift.
Concepts related to forward and reverse operation will now be discussed. There are two (2) states for a memory circuit: (i) forward state (also called an active state); and (ii) a reverse state (also called an idle state). An active state occurs when a clock input triggers the internal circuit chain elements to change from an idle state (reverse state) to the opposite state (forward state). At the end of memory access (as might be defined either by external clock itself by say, its falling edge, or by some internal timing circuit that will designate the end of the access) the memory circuits are returned to the idle state.